1. Field of Invention
This invention relates generally to techniques for treating parasitics in the design of integrated circuits. More specifically, it presents techniques that allow the design process to be aware of parasitics with varying degree of accuracy and also techniques allowing parasitics to be modeled during circuit design from the layout.
2. Description of Related Art
Radio frequency (RF) and High-Performance Analog designs are extremely sensitive to layout parasitic effects. With increased manufacturability challenges and aggressive performance goals, these parasitic effects are preferably taken into account early in the design cycle, during the circuit sizing and optimization process.
In a typical analog and mixed signal design methodology, the designer starts by designing the circuit in the absence of parasitics. At this point, the simulation tests point to the original schematic. Once the simulation outputs meet the expected goals, the designer proceeds to take parasitics into account. For most analog and mixed-signal designs, it is typically enough to estimate some of these parasitics on the schematic itself, manually. This is achieved by inserting some dummy parasitic elements into the schematic and analyzing the impact of these parasitics on the circuit performance. Once the schematic design meets design goals in the presence of simplistic schematic parasitic estimates, the design is handed off for layout. The parasitics are extracted from the finished layout using extraction tools. The extracted view is then used for a parasitic re-simulation flow that allows the verification of design goals post extraction.
Since RF and high-performance analog designs however are extremely sensitive to layout parasitics, the typical analog/mixed-signal methodology described above falls short because the final extracted design may not meet the design specifications and will often require a re-design and re-layout. As a result, there is a need for mechanisms to analyze the effects of parasitics early in the design flow, during the circuit simulation, circuit sizing and optimization.
Additionally, the electrical behavior of RF and high-performance analog designs is increasingly being affected by layout intricacies, forcing designers to account for these effects early in the design cycle. As current analog/mixed-signal design flows are mostly manual, relying on separate front-end design by a designer, who sizes the circuit schematic to meet performance goals, followed by hand-off to a layout engineer who places and routes the design. For most designs, the circuit may not meet all the specifications in the presence of layout parasitics, which are only detected after layout extraction, once the layout is complete. This makes it necessary to iterate multiple times between sizing and layout. To mitigate this problem, designers need to account for parasitics early in the design cycle, during circuit design and layout.
The existing approaches to estimate parasitics early in the design have been mostly manual and limited to parasitic estimation on the schematic. In some cases, the designer can manually enter RC estimate values for star-shaped net parasitic models. The designer can then simulate the circuit using predefined tests and compare the results from simulations with parasitics with that from simulations without parasitics. This approach is limited to analyzing parasitics estimated on the schematic. It does not offer any support for fetching parasitic information from layouts or partial layouts.
In other cases, the designer can extract parasitics from a layout using an extraction tool. The extracted view can then be used for parasitic re-simulation. For this approach, the layout needs to be completed and fully extracted using extraction tools. This is a time-consuming process. Further, the designers optimizing the circuit may not have all the skills to fully complete a layout and extract it, making this flow more cumbersome. Hence, there is a need for mechanisms that allow the designer to estimate parasitics from a layout, as the layout is being created, including parasitics from a partial layout. Further, none of these existing approaches allow the designer to mix-and-match schematic parasitic information with layout parasitic information.
With respect to the existing approaches to analyzing parasitics early in the design, these are mostly manual. The designer first simulates the circuit design without parasitics and saves the results from the simulation. The designer then inserts some dummy parasitic elements into the circuit schematic and simulates the circuit to analyze the impact of these parasitics on the circuit performance. The designer can then compare the results from simulations with parasitics with that from simulations without parasitics. When parasitics affect the circuit performance, the designer changes some of the sizes of the circuit elements to compensate for the presence of parasitics. However, sometimes when the design cannot meet the required performance targets, the designer might need to change the original circuit topology to achieve the desired performance goals and repeat the parasitic analysis steps. However, this process is typically very cumbersome and error-prone.
The described manual approach to perform parasitic analysis early in the design process is very cumbersome and error-prone. Since the designer has to manually insert dummy parasitics into the circuit schematic, it is very difficult to switch back-and-forth between these analyses types during the circuit design process and compare the results of simulations without parasitics with those of simulations.